(China (Mainland))
Product Summary
The EPM7064SLC44-10N is a high-density, high-performance PLD. It is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, it provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz.
Parametrics
Absolute maximum ratings: (1)VCC, Supply voltage With respect to ground: –2.0 to 7.0 V; (2)VI, DC input voltage: –2.0 to 7.0 V; (3)IOUT, DC output current, per pin: –25 to 25 mA; (4)TSTG, Storage temperature No bias: –65 to 150 ℃; (5)TAMB, Ambient temperature Under bias: –65 to 135 ℃; (6)TJ, Junction temperature Ceramic packages, under bias: 150 ℃ max; (7)PQFP, and RQFP packages, under bias: 135 ℃ max.
Features
Features: (1)High-performance, EEPROM-based programmable logic devices; (2)(PLDs) based on second-generation MAXR architecture; (3)5.0-V in-system programmability (ISP) through the built-in; (4)IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices; (5)Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices; (6)Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S; (7)devices with 128 or more macrocells; (8)Complete EPLD family with logic densities ranging from 600 to; (9)5,000 usable gates (see Tables 1 and 2); (10)5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect); (11)PCI-compliant devices available.
Diagrams
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 EPM7064SLC44-10N |
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IC MAX 7000 CPLD 64 44-PLCC |
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Other |
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EPM7032AELC44-10N |
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