(China (Mainland))
Product Summary
The EPM7160SQC160-10N is a Programmable Logic Device with advanced CMOS technology. It is based on Altera’s second-generation MAX architecture.
Parametrics
EPM7160SQC160-10N absolute maximum ratings: (1)Supply voltage With respect to ground:–2.0V to 7.0V; (2)DC input voltage:–2.0V to 7.0V; (3)DC output current, per pin:–25mA to 25mA; (4)Storage temperature No bias:–65℃ to 150℃; (5)Ambient temperature Under bias:–65℃ to 135℃; (6)Junction temperature Ceramic packages, under bias:150℃.
Features
EPM7160SQC160-10N features: (1)Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices; (2)Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more macrocells; (3)Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates (see Tables 1 and 2); (4)5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect); (5)PCI-compliant devices available; (6)Open-drain output option in MAX 7000S devices; (7)Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls; (8)Programmable power-saving mode for a reduction of over 50% in each macrocell; (9)Configurable expander product-term distribution, allowing up to 32 product terms per macrocell.
Diagrams
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